Level shifting circuits can translate an input signal that varies within one voltage range, to an output signal that varies within another, different voltage range. Typically, level shifting circuits can be utilized to translate between logic signals operating at different signal voltage levels (e.g., TTL to CMOS). Level shifting circuits for metal-oxide-semiconductor (MOS) type technologies, particularly CMOS type technology are well known.
In addition, “back biasing” MOS circuits are known that bias well or substrate regions of an integrated circuit to voltage levels less than ground. Such a back biasing of n-channel MOS transistors can reduce leakage in dynamic random access memory (DRAM) memory cell arrays, for example.
Co-pending U.S. patent application Ser. No. 11/452,442 filed on Jun. 13, 2006 and U.S. Provisional Patent Application Ser. No. 60/799,787 filed on May 11, 2006, both by Ashok K. Kapoor, show examples of novel circuits that include junction field effect transistors (JFETs) that operate at relatively low voltage levels (e.g., 0 to +0.5 volts). Such circuits can form integrated circuits that include few, or preferably no MOS type transistors. Accordingly, CMOS type level shifting circuits are of no benefit in shifting a low voltage internal signal (e.g., 0 to +0.5 volts) to some low output signal level (e.g., some negative voltage).